This argument is not pointless. I will not let you spread misinformation on the forums if I can help it, even if that means going off topic to correct you. To do otherwise is extremely unfair to many people. Some people might read what you type and think it's true. Then at some point in the future somebody will have to correct them and it will generate a lot of work for that somebody to purge the ideas from their head. Since many people can read your posts the problem is further compounded. On top of that you would likely repeat what you just told me somewhere else in the future and somebody else would try to correct you there. So I see no reason not to get it out of the way here. It benefits everyone.
We already thoroughly answered the OPs question and provided him with some tests to run but he hasn't responded in days so we have nothing to do until then. If he gets back and posts the results then we will of course resume the topic at hand.
Read the my last post. I guess you missed part of it (probably got ninja'd).
Quote: (probably got ninja'd)
Yup.
Quote:Damn it, my CS teacher needs to go get his degree again. He explained dual pumping as sending two signals in different directions, not on different edges of the clock (by which I mean rise/fall).
He was probably just making that BS up because he was too lazy to look it up. It happens a lot. This is why you should never trust your professors completely, especially the ones teaching introductory level classes, or god forbid, high school.
Quote:Half of my point stands, the other half falls. Companies do publish the "effective clock rate" (in this case what I believed to be 4200) while the actual clock rate is lower (what I believed to be 1050).
Does this sound right to you, then?
Fixed that for you. Now it's right.
Quote:However, the actual clock rate is not two signals going to directions, but two signals traveling along the same clock rise/fall cycle.
This is something I can't fix with a few quick bolded word replacements. This sentence is still completely wrong. Or rather it makes no sense.
Things I have a feeling you may not understand:
1. The clock signal is carried on a separate wire from the wires that carry the data. It exists to synchronize the bus on both ends and provide the necessary timing control for sampling.
2. You can have more than one clock signal for a bus. And you can have a bus with no clock signal. And yes clock signals can go in different directions on the same bus.
3. You can have more than one data signals as well. They too may or may not go in more than one direction.
4. In a double data rate bus the circuits on one or both sides of the bus sample the data on the bus twice per clock cycle instead of once. On both the rising and falling edge of each clock cycle. That's all it refers to.
DDR, DDR2, DDR3, VDDR (dual ported DDR), GDDR, GDDR2, GDDR3, GDDR4 are all examples of double pumped memory interface specifications. GDDR5 is an example of a quad pumped memory interface. XDR and XDR2 are octuple pumped memory bus specifications.
Ok. (Character limit)
I just remembered where all of his BS probably came from. No one in the CS department at my school actually has a CS degree. Everyone has a math degree (except this one guy with an art degree). They basically learned CS just to teach it to us. Most of them just say "read the book" but sometimes they explain (and in this case explain wrong).
(10-24-2012, 12:19 PM)NaturalViolence Wrote: [ -> ]What the hell are you talking about?
1. The bus standards don't define the number of channels. In graphics cards for example we have seen GDDR5 interfaces that are single channel (64 bit), dual channel (128 bit), triple channel (192 bit), quad channel (256 bit), and hexa channel (384 bit)
2. The number of channels doesn't affect the transfer rate in any way. It only affects the bus bitwidth, bandwidth, and throughput
3. EVGA is not reporting dual channel speeds. That makes no sense. The "speed" is usually either the data transfer rate or bandwidth.
I put "quad channel" and "dual channel" into quotation mark to emphasize it is indeed incorrect usage of the term.
As for evga ( or even msi afterburner ) for example lets take a gpu with gddr5 memory running at 1000mhz ( 4.0 Gbit/s )
These programs will report that as running at 2000 mhz.
How do you explain that ?
Its not data transfer rate nor bandwith
EDIT: Ok searched about this topic a little it turns out gddr5 runs at 2 different clocks ( frequencies )
WCK frequency is double of CK frequency,and it seems this WCK frequency is what is beeing reported in evga and msi instead of CK frequency
Quote:I put "quad channel" and "dual channel" into quotation mark to emphasize it is indeed incorrect usage of the term.
But they don't use it that way either.
Quote:EDIT: Ok searched about this topic a little it turns out gddr5 runs at 2 different clocks ( frequencies )
Be careful how you word that. It uses two write clock signals but they both run at the same frequency.
If you want to be even more technical it has 6 clock signals.
WCLK0
WCLK0 Differential
WCLK1
WCLK1 Differential
CK
CK Differential
Since it uses differential signaling. WCLK1 are 180 degrees out of phase from WCLK0 to achieve double pumping.
Quote:WCK frequency is double of CK frequency,and it seems this WCK frequency is what is beeing reported in evga and msi instead of CK frequency
Ding ding ding ding. Now you're getting it.
Command Clock: 1050MHz
Write Clock: 2100MHz
Data transfer rate: 4200 MT/s
Ratio of data transfers to command clock cycles: 4, therefore it's considered quad data rate