01-29-2011, 06:08 AM
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01-29-2011, 06:11 AM
The same way Intel supports MMX but not 3DNow
or AMD supports SSE4a, but not SSSE3.
or how bulldozer supports AVX and SSE4 but not SSSE3.
There are some pretty much functionally similar instructions in SSE4 that for some reason take longer to execute, than doing it with SS(S)E3.
Intel does not have to include maintain these instruction sets forever, they choose to do so (and at this point dropping SSE would break alot of Drivers)
And if you throw AVX into the mix, you actually lose out by a small load/restore overhead when mixing SSE and AVX instructions.
or AMD supports SSE4a, but not SSSE3.
or how bulldozer supports AVX and SSE4 but not SSSE3.
There are some pretty much functionally similar instructions in SSE4 that for some reason take longer to execute, than doing it with SS(S)E3.
Intel does not have to include maintain these instruction sets forever, they choose to do so (and at this point dropping SSE would break alot of Drivers)
And if you throw AVX into the mix, you actually lose out by a small load/restore overhead when mixing SSE and AVX instructions.
01-29-2011, 06:16 AM
thanks for the info. Good to know.
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