fringle Wrote:Maybe it has something to do with the way AMD cpu's share resources among cores
Correct. The L1I cache, L2 cache, and FPU are all shared at the module level.
It depends on which cores you enabled/disable. Each pair of logical cores that you see is actually one physical core at the silicon level. Similar to HT.
If you were to disable cores 3-6 for example both remaining threads would be forced to share the same physical core. If you were to disable cores 2, 4, and 6 however it should have no performance hit.
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-Ron Swanson
"I shall be a good politician, even if it kills me. Or if it kills anyone else for that matter. "
-Mark Antony