CPU Microarchitecture Hierarchy

[NaturalViolence]

>Open for one day
>13 votes for, 1 vote against
>93% want me to do it

Well I guess I am socially obligated to do it now.

I will make an adjusted clock rate multiplier for adjusting relative performance based on IPC. This would be a lot easier if I could make tables, but lack of HTML support makes that borderline impossible.

[NaturalViolence]

An update:
After beginning work on the initial diagrams and article for the post I quickly realized that the guide would be utterly useless to the average reader who would not understand most of the terminology. So I focused on my other hierarchy thread instead and began writing a glossary of terms for this thread. But as usual I went too far. Due to my OCD for completeness the glossary of terms became long, boring, and difficult to understand. Believe it or not the original glossary of terms was twice as long. I think what I'm going to do is copy the glossary of terms onto my website and remove all non-essential terms in this thread. I added some helpful images to help clarify some of the definitions and plan to add more in the future.

But I now realize that due to my general lack of motivation in this thread as well as lack of time I'm going to need some help to finish this. All I need from one lucky volunteer (by which I mean anyone willing to help me) is a version of this image:


but for AMD cpus. I will of course provide all of the data that you need. I don't care how you do it and it doesn't have to look identical. I would however like it to maintain a similar style. The image will also be uploaded by either you or me to wikipedia. Is anyone interested in helping me be lazy?

[dEnigma]

I realize this was posted a long time ago but did you already find someone to help you?

[NaturalViolence]

I actually did. He did it but I wasn't quite satisfied with it (there were still a few things that needed to be added and changed). I forgot to email him back. And that was months ago. I'll get around to it eventually. Why are you interested?

[dEnigma]

I just thought that I could do that job if nobody had volunteered. Just send me a message if your guy doesn't want to work on it anymore.

[NaturalViolence]

He hasn't been on the forums in half a year. I'm sure he wouldn't mind if you edited it considering he gave me permission to use it as I like. Plus I don't want to bother him again when he already did so much. I'll just add his name to it when it's ready to be posted to give him credit. I attached the .svg he sent me. It's been so long that I can't exactly remember everything that needed to be changed. I suddenly became very busy one week and then forgot all about it. I'll have to go through those old PMs and take a look. He did a good job but it still needs some adjustments.

As you can see it's too big. Way too big. And some of the colors make the text difficult to read (the red and yellow text in particular).

Spelling errors:
Thornton should be Thorton

Position:
Thoroughbred, Barton/Thorton needs to be shifted a bit to the right so that it is completely inside 130nm.
Shift Toledo/Manchester to the right so it lines up with Sandiego/Venice

Rename:
K10 to 10H

Remove:
Excavator, just get rid of it
The stars and husky color coding, for now.

Ultimately I want this organized a bit more neatly into rows/columns that are aligned. Which is why I listed "empty" to indicate empty slots. He seems to have used center align in each manufacturing process column. I want them spaced out so that they align in rows and columns (without grid lines). Read the PM below and hopefully you'll know what I mean. Look at the part that talks about layers in particular.

I'm curious to see what you can pull off. I'll do a more thorough error check soon.

Part of PM detailing instructions, use as a reference: (Show Spoiler)

Try to replicate the style if you can.



We're going to start at 180nm just like the Intel chart but we're only
going to go up to 28nm since AMD hasn't released any info. about
anything past that on their roadmap yet. There are two extra
manufacturing processes that Intel doesn't use, 40nm and 28nm. Your
manufacturing process (the bottom) slots will need to be much wider. On
Intels chart there are only at max 2 chips per manufacturing process but
with AMD there are sometimes over half a dozen. The manufacturing
process slots all need to be equally wide and all need to be wide enough
to accommodate 4 chip codenames. The widest will be 130nm which has
Thoroughbred + Barton/Thorton from K7 and Sledgehammer +
Clawhammer/Newcastle from K8 (4 slots total). Also 65nm will use all 4
slots.



The microarchitecture boxes must be different colors just like the Intel flowchart.



There is not going to be any names in red font or blue font so you can get rid of the font color legend in the upper right.





Microarchitecture (the boxes) List:

K7 (180nm, 130nm)

K8 (130nm, 90nm, 65nm)

K10 (65nm 45nm, 40nm, 32nm)

Bulldozer (32nm 28nm)

Bobcat (40nm, 32nm, 28nm)



This is all of the microarchitectures in order and the manufacturing
process slots that they occupy (so that you know how far the box needs
to stretch).



Manufacturing Process List:

180nm (K7)

130nm (K7, K8)

90nm (K8)

65nm (K8, K10)

45nm (K10)

40nm (K10, bobcat)

32nm (K10, bulldozer, bobcat)

28nm (bulldozer, bobcat)



This is the inverse. A list of all of the manufacturing processes slots
in order and the microarchitecture boxes in them. As you can see the
boxes will overlap a bit so you will need to stack them on top of one
another like the Intel flowchart. I don't care which direction you stack
them in. As you can see at 32nm you will have three boxes stacked on
top of each other.



I suggest you make the boxes first then move onto stage 2 (filling them
in with the codenames) since that would probably be easiest. Everything
above this sentence is stage 1, everything below it is stage 2.



K7

180nm (Pluto/Orion, Thunderbird, Palomino)

130nm (Thoroughbred, Barton/Thorton)



1 layer tall with all 5 in a single straight line. Pluto/Orion, Thunderbird, Palomino, Thoroughbred, Barton/Thorton



K8

130nm (Sledgehammer, Clawhammer, Newcastle)

90nm (Winchester, Venice, San Diego, Manchester, Orleans, Toledo, Windsor)

65nm (Lima, Brisbane)



Yes there are 7 90nm architectures. Take a look at the Core
microarchitecture (box) in the Intel chart. See how they have two layers
stacked inside the box? The top layer is Conroe and wolfdale, the
bottom layer is kentsfield and yorkfield. I want you to do the same
thing here. Both layers are inside the K8 box.



Top Layer: Empty, Empty, Empty, Toledo/Manchester (90nm), Windsor (90nm), Brisbane (65nm)

Bottom layer: Sledgehammer (130nm), Clawhammer/Newcastle (130nm),
Winchester (90nm), San Diego/Venice (90nm), Orleans (90nm), Lima (65nm)



This will get you down to 3 slots at the 90nm manufacturing process
instead of 7. Each layer will have 6 slots (counting the empty slots). I
would advise from here on out that you ignore the part right below the
microarchitecture name where I list everything by manufacturing process
and skip to the part where I list the layers since it's less confusing
to read it by layer.



K10

65nm (Agena, Toliman, Kuma)

45nm (Thuban, Zosma, Deneb, Heka, Callisto, Propus, Rana, Regor, Sargas)

40nm Nothing, just draw a line through it

32nm (Llano (A8), Llano (A6), Llano (A4), Llano (E2))



Once again you would have 9 names in one manufacturing process if you
did it as a single layer. This one will be broken into 5 layers.



Top Layer: Empty, Thuban (45nm), Empty

Upper Middle: Agena (65nm), Deneb/Zosma/Propus (45nm), Llano (A8) (32nm)

Middle: Toliman (65nm), Heka/Rana (45nm), Llano (A6) (32nm)

Lower Middle: Kuma (65nm), Callisto/Regor (45nm), Llano (A4) (32nm)

Bottom: Empty, Sargas (45nm), Llano (E2) (32nm)



Make sure to list Llano (A4) for example instead of just Llano. I know it's confusing with the two sets of parenthesis.



Bulldozer

32nm (Zambezi, Vishera, Trinity)

28nm (Excavator, Kaveri)



Two layers.



Top Layer: Zambezi (32nm), Vishera (32nm), Excavator (28nm)

Bottom layer: Empty, Trinity (32nm), Kaveri (28nm)



Bobcat

40nm (Desna, Ontario, Zacate, Hondo, Brazos 2.0)

32nm Nothing, just draw a line through it

28nm (Kabini, Temash)



3 layers.



Top Layer: Zacate (40nm), Brazos 2.0 (40nm), Kabini (28nm)

Middle Layer: Ontario (40nm), Empty, Kabini (28nm)

Bottom Layer: Desna (40nm), Hondo (40nm), Temash (28nm)



Now for the third and final stage. Remember that part where I told you
to get rid of the font color legend? I lied. Just like before the
microarchitecture names will be in grey font and the chip names will be
in black font. Make sure to include that on the font legend. Next I want
you to come up with 7 additional font colors of your choice. Now create
a font legend with the following 7 names:

Stars, Husky, Bulldozer, Piledriver, Steamroller, Bobcat, Jaguar



Each one will be colored something different the same way the Intel flowchart had it.



Now color code the cooresponding chip names.



First go to the K10 box.

Everything in the first column (slot) and second column will be stars. Everything in the third column is husky.



Now go to the bulldozer box.

The first column is bulldozer. The second column is piledriver. The third column is steamroller.



Now the Bobcat box.

First and second column are bobcat. Third column is jaguar.



Now you're finally done.

[dEnigma]

Okay, just give me some time, I'll try to show you some results by this weekend.

edit: But please don't expect any design magic from me

edit2: One question right away: Is it a problem if I make those boxes a little bigger in the y-axis, because the whole column idea is a little hard to accomplish with boxes that have such little height, while maintaining readability (legibility? What is the right word here? )

[NaturalViolence]

Sure. And yes legibility works in that sentence.