Compiling Win32 ARM64

Gerdya · 03-29-2018, 08:24 PM **#13**

(03-29-2018, 05:08 PM)degasus Wrote: Oh nice. You've made my day. Feel free to create PRs for such patches. About your JIT issue, just revert https://github.com/dolphin-emu/dolphin/pull/4204 and it may work. Our libc cache invalidation was broken on Exynos as they have different cache line sizes on the big/little cluster.

I did make an assembly implementation for flush. It should reflect pretty much the C/intrinsic version (unless i made a mistake).

Code:

    EXPORT    |_FlushIcacheSection|

    AREA    |.text$mn|, CODE, ARM64

|_FlushIcacheSection| PROC

    mrs   x3, CTR_EL0                            ;x3 = ctr_el0

    mov   x5, #4

    mov   x6, #0xf

    and   x4, x3, x6                        

    lsl   x4, x5, x4                            ; isize = 4 << ((ctr_el0 >> 0) & 0xf) -> x4

    and   x3, x6, x3, lsr #16

    lsl   x3, x5, x3                            ; dsize = 4 << ((ctr_el0 >> 16) & 0xf) -> x3

    sub   x5, x31, x3

    and   x6, x0, x5                            ; addr = (u64)start & ~(u64)(dsize - 1);

dcache

    dc    civac, x6

    add   x6, x6, x3                            ; addr += dsize

    cmp   x6, x1

    blt   dcache                                    ; addr < end

    dsb   ish

    sub   x5, x31, x4

    and   x6, x0, x5                            ; addr = (u64)start & ~(u64)(isize - 1);

icache

    ic    ivau, x6

    add   x6, x6, x4                            ; addr += isize

    cmp   x6, x1                                    

    blt   icache                                    ; addr < end

    dsb   ish

    isb

    ret 

    ENDP  ; |_FlushIcacheSection|

    END

It does ask for both cache lines size of I$ and D$ via CTR_EL0.
And then modified ARM64XEmitter:

Code:

void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)

{

  if (start == end)

    return;

#if defined(IOS)

  // Header file says this is equivalent to: sys_icache_invalidate(start, end - start);

  sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);

#elif defined _MSC_VER

  //MSC does not support inline assembly for ARM64

  //instead an assembly implementation in Arm64Emitter_util.asm is called

  _FlushIcacheSection(start, end);

#else

But i still get a Bluescreen when enabling JIT. Well i need to wait for device since debugging with QEmu is not possible at the moment.